The present invention relates generally to sequentially addressing a memory device and, more particularly, to providing a fault-tolerant redundant addressing mechanism for sequentially addressing memory arrays.
Many computing systems such as personal computers, automotive and airplane control, video cameras, digital cameras, cellular phones, and handheld communication devices use nonvolatile writeable memories to store either data, or code, or both. Such nonvolatile writeable memories include Electrically Erasable Programmable Read-Only Memories (EEPROMs) and flash Erasable Programmable Read-Only Memories (flash EPROMs, or flash memories). Nonvolatility is advantageous for allowing the computing system to retain its data and code when power is removed from the computing system. Thus, if the system is turned off or if there is a power failure, there is no loss of code or data.
Nonvolatile semiconductor memory devices are fundamental building blocks in prior art computer system designs. The primary mechanism by which data is stored in nonvolatile memory is the memory cell. One type of prior nonvolatile semiconductor memory is the flash electrically-erasable programmable read-only memory (flash EEPROM). Prior art flash EEPROMs typically allow for the simultaneous reading of several flash cells. Further, typical prior art flash EEPROMs have a storage capacity that is much greater than the amount of data that can be output at any one time. Accordingly, each output of a flash EEPROM is typically associated with an array of flash cells that is arranged into rows and columns, where each flash cell in an array is uniquely addressable. When a user provides an address, row and column decoding logic in the flash EEPROM selects the corresponding flash cell.
FIG. 1 is a block diagram of a prior art system 100 including nonvolatile writeable memory. This system includes a microcontroller or digital signal processor (DSP) 102 and system components 104-108. System components 104-108 can be any other electronic components of the system 100 which, for example, might include but are not limited to additional memory components like static random access memory (SRAM), EPROM, and EEPROM. The microcontroller or DSP 102 communicates with the nonvolatile writeable memory 110 via address lines 118 and input/output (I/O) data lines 120. A power supply 112 provides a voltage on line 114 to the nonvolatile writeable memory 110 as well as to the system microcontroller or DSP 102, and system components 104-108.
FIG. 2 is a typical prior art nonvolatile writeable memory device 110. This memory device 110 comprises a two-dimensional array of single-bit memory cells 202. A first dimension is defined by sense lines 204 that carry data from any row in the array to the input/output (I/O) connections. The number of sense lines 204 may range from one to the number of columns in the array. A second dimension is defined by word lines 0-N that identify which row of the array will be sensed by the sense lines. Typical prior art decoding logic provides that these word lines are typically controlled by an address decoder 206 so that a row number encoded as an address can be used to selectively enable a row in the array. The address decoder 206 provides random access to the memory cells 202 of the two-dimensional array by decoding the address inputs 118 to a unique word line and enabling that corresponding group of memory cells to be read or written using the sense lines 204.
For a typical time-based data type, or streaming data type, a memory device that provides linear access is fundamentally more efficient than one which offers random access. Streaming data types include, but are not limited to, video image data, still image data, audio data, and other natural data types. Linear access is more efficient because linear access is inherently simpler to implement. With the recent proliferation of digital cameras and other devices used for capturing natural data types using digital storage media, there has been a significant rise in the use of flash memory for digital storage of this data. The problem is that because flash memory is typically considered as an evolution of other types of random-access computer memory, it is typically implemented in a streaming data type application using the random access provided by an address decoding addressing mechanism, even though the random access is not necessary. This increases the cost and complexity of the time-based data device while decreasing the efficiency of the device.
A prior art exception to the typical random access solid state memory device is the first-in, first-out (FIFO) memory device. The FIFO memory is typically formed from shift registers used in parallel. These register memories typically have independent input and output buses. At the input port, data is controlled by a shift-in clock operating in conjunction with an input ready signal which indicates whether the memory is able to accept further words or is now full. The data entered is automatically shifted in parallel to the adjacent memory location if it is empty and as this continues the data words stack up at the output end of the memory. At the output port, data transfers are controlled by a shift-out clock and its associated output ready signal. The output ready signal indicates either that a data word is ready to be shifted out or that the memory is now empty. The FIFO memory can be cascaded to any desired depth and operated in parallel to give any required word length. Due to the nature of the program and erase operations in nonvolatile writeable memories, however, the FIFO data accessing scheme is not viable because it does not provide any memory cell redundancy.
Memory cell redundancy is used in typical prior art nonvolatile writeable memory to reduce the impact of memory cell failure during the use or manufacture of the memory. Memory cell failure can occur in nonvolatile writeable memory as a result of the continuous application of voltage in the programming and erasing of memory cell transistors. Memory cell redundancy is the process wherein extra cells comprising bit lines and word lines, and the associated multiplexing circuitry, are included in the memory array. In the event of a failure of memory cells of the array, the redundant cell lines or cell blocks are mapped into the memory array to replace the failed memory cells and provide a memory array that is 100% functional. The problem with providing redundant memory cells in a memory array is that the redundant cells consume valuable silicon area as well as increase the cost of the memory device.
A memory comprising an addressing circuit is provided. The addressing circuit comprises at least one sequential shift register and at least one corresponding logic gate and at least one corresponding word flag cell coupled to each of the memory word lines. Enablement of the each memory word line depends upon the state of the word flag cell.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description and appended claims that follow below.